1. Field of the Invention
The present invention relates in general to electronic memories and in particular to methods and circuits for single-memory cell multivalued data storage.
2. Description of Related Art
Current processing systems operate on binary data wherein a logic 1 is represented by a high voltage level (approximately Vcc, typically 3.3 or 5V) and a logic 0 is represented by a low voltage level (approximately Vss, typically 0V or ground). Consequently, conventional random access memory cells, dynamic (DRAM) or static (SRAM) charge a cell capacitor to the high voltage level to store a logic 1 and discharge the capacitor to the low voltage level to store a logic 0. During a read in DRAM's, the voltage on the cell capacitor (which may have drifted due to leakage) is differentially sensed against a reference voltage set between Vcc and Vss and then, depending on the result, restored by latching to the full Vcc or Vss level. Data from the cell is similarly output to the periphery and ultimately outside the DRAM device itself by driving various input/output (I/O) lines to approximately Vcc or Vss.
One of the main thrusts of current DRAM development efforts is to provide for the storage of more bits per DRAM chip (storage capacity). One means for accomplishing this goal is to increase DRAM cell density (i.e., the number of cells per given chip area). This requires the development of advanced circuit design and fabrication techniques to pack smaller cells into denser arrays, which is a time consuming process. Further, as DRAM cells become smaller and the arrays more dense, device physics increasingly become a limiting factor in the pace of progress in the development of new DRAMs. In any event, the development of new high cell-density DRAMs may take years to advance the design from theory to a commercially viable product.
Proposals have been made to increase memory capacity (for both volatile memory, such as DRAM, and non-volatile memory such as flash memory) by storing multiple bits per cell. In one approach, more than the traditional two voltage levels can be impressed on the storage mechanism of a cell, with each voltage level representing a different data value. For example, assume that for a given cell, data can be stored as one of four allowed voltage levels. A voltage of 0V can then be used to represent a two bit logic word "00", a voltage of 1V to represent a logic "01", a voltage of 2V to represent a logic "10" and a voltage of 3V to represent a logic "11". In this fashion, an MSB and an LSB can be stored in a single cell. The exact voltages and the number of voltage levels used vary from scheme to scheme.
The actual implementation of these multivalued memories presents a number of problems. For instance, Murotani et al. (1997 IEEE International Solid State Circuit Conference, Digest of Technical Papers, pp 74-75, 1997) have proposed a 4-level storage device in which both an MSB and an LSB can be stored in a single cell as a function of capacitor voltage. Disadvantageously, this scheme requires two sense and restore cycles be performed during a read operation, one to sense the cell capacitor voltage against a first reference voltage to detect the MSB, and a second to sense the cell capacitor voltage against a second reference voltage to detect the LSB. At a minimum, this scheme results in greater DRAM latency, which is already at a premium for most state of the art applications not to mention a complex sense restore scheme. Further, the Murotani circuitry is more complex and consumes more space on the integrated circuit chip. Among other things, two sense amplifiers are now required to support the two sensing cycles, additional transfer gates and capacitors are required to set the bitlines to the proper reference voltages, and the memory cell capacitors must be two to three times larger to account for leakage and other losses due to the dual sensing cycle approach.
In addition to the problem of sensing, multiple level storage systems face a number of other problems which also must be addressed. For example, current digital I/O buffers are designed only to drive/receive data at high and low voltage levels and not data at one of n number of voltage levels (n greater than two). Similarly, all current PC processing components (e.g. CPUs, core logic, buses) are also designed to operate on digital (binary) data.
A need has therefore arisen for new circuitry and methods for implementing multivalued storage. The problem of accurately and quickly sensing data is one primary concern that must be addressed. To this end, the task of minimizing the size and complexity of the necessary circuitry cannot be ignored. Additionally, such circuitry and methods should be compatible with current digital devices and systems.